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71M6543F/71M6543G Data Sheet
FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not automatically reset. It should be cleared when the SPI or
ICE has finished changing the Flash. Table 40 summarizes the I/O RAM registers used for flash security.
Table 40: Flash Security
Name
FLSH_UNLOCK[3:0]
SECURE
Location
2702[7:4]
SFR B2[6]
Rst
0
0
Wk
0
0
Dir
R/W
R/W
Description
Must be a 2 to enable any flash modification.
See the description of Flash security for
more details.
Inhibits erasure of page 0 and flash addresses
above the beginning of CE code as defined
by CE_LCTN[6/5:0] (I/O RAM 0x2109[5:0]) on
the 71M6543F and CE_LCTN[6:0] I/O RAM
0x2109[6:0]) on the 71M6543G . Also inhibits
the read of flash via the ICE and SPI ports.
SPI Flash Mode
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6543 contains a Special Flash Mode (SFM) that facilitates initial (production) programming of the
flash memory. When the 71M6543 is in SFM mode, the SPI interface can erase, read, and write the
flash. Other memory elements such as XRAM and I/O RAM are not accessible to the SPI in this mode.
In order to protect the flash contents, several operations are required before the SFM mode is successfully
invoked.
When the 71M6543G is operating SFM, SPI single-byte transactions are used to write to FL_BANK[1:0]
(SFR 0xB6[1:0]) . During an SPI single-byte transaction, SPI_CMD[1:0] will over-write the contents of
FL_BANK[1:0] (SFR 0xB6[1:0]) . This will allow for access of the entire 128 KB flash memory while
operating in SFM.
If the SPI port is used for code updates (in lieu of a programmer that uses the ICE port), then a code that
disables the flash access via SPI can potentially lock out flash program updates.
Details on the SFM can be found in 2.5.12 SPI Slave Port .
2.5.1.2 MPU/CE RAM
The 71M6543 includes 5 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the
MPU core. The 5KB of static RAM are used for data storage by both MPU and CE and for the
communication between MPU and CE.
2.5.1.3 I/O RAM (Configuration RAM)
The I/O RAM can be seen as a series of hardware registers that control basic hardware functions. I/O
RAM address space starts at 0x2000. The registers of the I/O RAM are listed in Table 68 .
The 71M6543 includes 128 bytes non-volatile RAM memory on-chip in the I/O RAM address space
(addresses 0x2800 to 0x287F). This memory section is supported by the voltage applied at VBAT_RTC,
and the data in it are preserved in BRN, LCD, and SLP modes as long as the voltage at VBAT_RTC is
within specification.
2.5.2
Oscillator
The 71M6543 oscillator drives a standard 32.768 kHz watch crystal. This type of crystal is accurate and
does not require a high-current oscillator circuit. The oscillator has been designed specifically to handle
watch crystals and is compatible with their high impedance and limited power handling capability. The
oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to 2.5.4, Real-Time
Clock (RTC) for more information.
The oscillator is powered from the V3P3SYS pin or from the VBAT_RTC pin, depending on the V3OK
internal bit (i.e., V3OK = 1 if V3P3SYS ≥ 2.8 VDC and V3OK = 0 if V3P3SYS < 2.8 VDC). The oscillator
requires approximately 100 nA, which is negligible compared to the internal leakage of a battery.
48
v2
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